VHDL frekvencije

[manac5800]

Pozdrav
Trebam napisati VHDL (u Xilinxu, ako igra ikakvu ulogu) za sklop koji na izlazu daje frekvenciju 0, 100, 200, 300 ili 400 Hz. Zeljena frekvencija se odabire pomocu prekidaca na Spartan razvojnom sustavu, i prikazuje se na ugrađenim 7 segmentnim displayima..
E sad, napravio sam "module" ili podprograme za svaku od frekvencija, jednostavno kao djelitelje frekvencije, npr za 200Hz:

Code: Select all

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity frek0 is
    Port ( cp : in  STD_LOGIC;
           cp_0 : buffer STD_LOGIC);
end frek0;

architecture Behavioral of frek0 is

begin
cp_0<='0';

end Behavioral;

Dalje, napravio sam i podprogram za svaki prikaz na displayima, opet za 200Hz:

Code: Select all

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity display200 is
  Port ( cp_in : in std_logic;
         AN3 : inout std_logic;
         AN2 : inout std_logic;
         AN1 : inout std_logic;
         AN0 : inout std_logic;
         led : out std_logic_vector(6 downto 0));
end display200;

architecture Behavioral of display200 is

signal brojac : STD_LOGIC_VECTOR(12 downto 0);
begin			
  process (cp_in)
  begin
    if cp_in'event and cp_in = '1' then
      if (brojac="0000000000000") then
        if (AN0='0') then 
          AN0 <= '1';	 
          led <= "1000000";             -- 0
          AN1 <= '0';
        elsif (AN1='0') then 
          AN1 <= '1';	 	 
          led <= "1000000";             -- 0
          AN2 <= '0';
        elsif (AN2='0') then 
          AN2 <= '1';	 
          led <= "0100100";             -- 2
          AN3 <= '0';
        elsif (AN3='0') then 
          AN3 <= '1';
          led <= "1111111";             -- ugasen
          AN0 <= '0';
        end if;
      end if;
      brojac<=brojac+"0000000000001";
      if (brojac > "1000000000000") then
        brojac<="0000000000000";
      end if;
    end if;
  end process;
end Behavioral;

E sad me zanima je li bolje:
1. odmah svaki "prikaz displaya" staviti u "odabranu frekvenciju"
2. da "odabrana frekvencija" poziva podprogram "prikaz displaya"
ili 3. da glavni program (top module) poziva oba podprograma

I što koristiti za sam tok programa? if, switch-case, signal...?
Meni je switch-case nekako najprivlačniji, ali nisam ga koristio dosad baš pa mi je malo problem...
Hvala unaprijed!

[manac5800]

evo ovako sam "glavni" program napisao:

Code: Select all

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity glavni is
port (	cp, sw0, sw1, sw2 : in  std_logic;
         frek : buffer  std_logic;
			AN3 : inout std_logic;
			AN2 : inout std_logic;
         AN1 : inout std_logic;
         AN0 : inout std_logic;
         led : out std_logic_vector(6 downto 0));
end glavni;

architecture Behavioral of glavni is
signal co0,co100,co200,co300,co400 : std_logic;
signal led0,led100,led200,led300,led400 : std_logic_vector (6 downto 0);

begin
s1: entity frek0 port map (cp,co0);
s2: entity frek100 port map (cp,co100);
s3: entity frek200 port map (cp,co200);
s4: entity frek300 port map (cp,co300);
s5: entity frek400 port map (cp,co400);
s6: entity display0 port map (cp,AN3,AN2,AN1,AN0,led0);
s7: entity display100 port map (cp,AN3,AN2,AN1,AN0,led100);
s8: entity display200 port map (cp,AN3,AN2,AN1,AN0,led200);
s9: entity display300 port map (cp,AN3,AN2,AN1,AN0,led300);
s10: entity display400 port map (cp,AN3,AN2,AN1,AN0,led400);

process(sw0,sw1,sw2)
begin
if(sw0<='0' and sw1<='0' and sw2<='0') then
frek<=co0;
led<=led0;
elsif (sw0<='1' and sw1<='0' and sw2<='0') then
frek<=co100;
led<=led100;
elsif (sw0<='0' and sw1<='1' and sw2<='0') then
frek<=co200;
led<=led200;
elsif (sw0<='1' and sw1<='1' and sw2<='0') then
frek<=co300;
led<=led300;
elsif (sw0<='0' and sw1<='0' and sw2<='1') then
frek<=co400;
led<=led400;
end if;
end process;
end Behavioral;

Valja/ne valja? :O
Itko? :O